// the tech social -> Verilog Programming 
// half adder module 
module half_adder (
    input a, b,
    output sum, carry
);
    assign sum = a ^ b;   // sum of half adder
    assign carry = a & b; // carry of half adder
     
endmodule
 
// the tech social -> Verilog Programming
// full adder module
module full_adder (
    input a, b, cin,
    output sum, cout
);
    assign sum = a ^ b ^ cin;
    assign cout = (a & b) | (cin & (a ^ b));
 
endmodule
 
// the tech social -> Verilog Programming
// N-bit adder module
// here let N = 8 => 8-bit adder
module N_bit_adder 
#(parameter N = 8)
(
    input [N-1:0] input1, 
    input [N-1:0] input2,
    output [N-1:0] answer,
    output carry_out // Define carry_out as an output
);
    wire [N-1:0] carry; // Intermediate carry outputs
    
    genvar i; // General variable

    generate
        for (i = 0; i < N; i = i + 1) begin: generate_N_bit_adder
            if (i == 0) // LSB bit adder
                half_adder b (
                    .a(input1[i]), 
                    .b(input2[i]), 
                    .sum(answer[i]), 
                    .carry(carry[i])
                );
            else // Rest all adders
                full_adder b (
                    .a(input1[i]), 
                    .b(input2[i]), 
                    .cin(carry[i-1]), 
                    .sum(answer[i]), 
                    .cout(carry[i])
                );
        end   
        assign carry_out = carry[N-1]; // Carry out assignment
    endgenerate
endmodule